1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional vertical memory (3D-MV).
2. Prior Arts
Three-dimensional memory (3D-M) is a monolithic semiconductor memory comprising a plurality of vertically stacked memory cells. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). 3D-M may further be a 3D-memristor, 3D-RRAM or 3D-ReRAM (resistive random-access memory), 3D-PCM (phase-change memory), 3D-PMC (programmable metallization-cell memory), or 3D-CBRAM (conductive-bridging random-access memory).
U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-M, more particularly a 3D-ROM. As illustrated in FIG. 1A, a 3D-M die 20 comprises a substrate-circuit level 0K and a plurality of vertically stacked memory levels 16A, 16B. The substrate-circuit level 0K comprises substrate transistors 0t and substrate interconnects 0i. The substrate transistors 0t are formed in a semiconductor substrate 0. The substrate interconnects 0i are the interconnects for the substrate transistor 0t. In this example, the substrate interconnects 0i includes metal layers 0M1, 0M2. Hereinafter, the metal layers 0M1, 0M2 in the substrate interconnects 0i are referred to as substrate interconnect layers; the materials used in the substrate interconnects 0i are referred to as substrate interconnect materials.
The memory levels 16A, 16B are stacked above the substrate-circuit level 0K. They are coupled to the substrate 0 through contact vias (e.g., 1av). Each of the memory levels (e.g., 16A) comprises a plurality of upper address lines (e.g., 2a), lower address lines (e.g., 1a) and memory cells (e.g., 5aa). The memory cells could comprise diodes, transistors or other devices. Among all types of memory cells, the diode-based memory cells are of particular interest because they have the smallest size of ˜4F2, where F is the minimum feature size. Since they are generally located at the cross points between the upper and lower address lines, the diode-based memory cells form a cross-point array. Hereinafter, diode is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. In one exemplary embodiment, diode is a semiconductor diode, e.g., p-i-n silicon diode. In another exemplary embodiment, diode is a metal-oxide diode, e.g., titanium-oxide diode, nickel-oxide diode.
The memory levels 16A, 16B form at least a 3D-M array 16, while the substrate-circuit level 0K comprises the peripheral circuit for the 3D-M array 16. A first portion of the peripheral circuit is located underneath the 3D-M array 16 and it is referred to as under-array peripheral circuit. A second portion of the peripheral circuit is located outside the 3D-M array 16 and it is referred to as outside-array peripheral circuits 18. Because the outside-array peripheral circuit 18 comprises significantly fewer back-end-of-line (BEOL) levels than the 3D-M array 16, the space 17 above the outside-array peripheral circuits 18 is empty and completely wasted. Hereinafter, a BEOL level refers to a level of conductive lines above the substrate. In FIG. 1A, the 3D-M array 16 comprises a total of six BEOL levels, including the two interconnect levels 0M1, 0M2, two address-line levels 1a, 2a for the first memory level 16A, and two address-line levels 3a, 4a for the second memory level 16B. The outside-array peripheral circuit 18 comprises only two BEOL levels, i.e., the interconnect levels 0M1, 0M2.
U.S. Pat. No. 7,383,476 issued to Crowley et al. on Jun. 3, 2008 discloses an integrated 3D-M die, whose 3D-arrays and peripheral circuit are integrated on a single die. As is illustrated in FIG. 1 B, an integrated 3D-M die 20 comprises a 3D-array region 22 and a peripheral-circuit region 28. The 3D-array region 22 comprises a plurality of 3D-M arrays (e.g., 22aa, 22ay) and their decoders (e.g., 24, 24G). These decoders include local decoders 24 and global decoders 24G. The local decoder 24 decodes address/data for a single 3D-M array, while the global decoder 24G decodes global address/data 25 to each 3D-M array.
The peripheral-circuit region 28 comprises all necessary peripheral-circuit components for a standalone integrated 3D-M die 20 to perform basic memory functions, i.e., it can directly use the voltage supply 23 provided by a user (e.g., a host device), directly read data 27 from the user and directly write data 27 to the user. It includes a read/write-voltage generator (VR/VW-generator) 21 and an address/data (A/D)-translator 29. The VR/VW-generator 21 provides read voltage VR and/or write (programming) voltage VW to the 3D-M array(s). The A/D-translator 29 converts address and/or data from a logical space to a physical space and/or vice versa. Hereinafter, the logical space is the space viewed from the perspective of a user of the 3D-M, while the physical space is the space viewed from the perspective of the 3D-M.
The example in FIGS. 1A-1B is a three-dimensional horizontal memory (3-MH), whose basic storage units are horizontal memory levels. The above description can also be applied to a three-dimensional vertical memory (3D-MV), whose basic storage units are vertical memory strings.
U.S. Pat. No. 8,638,611 issued to Sim et al. on Jan. 28, 2014 discloses a 3D-MV. It is a vertical-NAND. Besides vertical-NAND, the 3D-ROM, 3D-RAM, 3D-memristor, 3D-ReRAM or 3D-RRAM, 3D-PCM, 3D-PMC, 3D-CBRAM can also be arranged into 3D-MV. As illustrated in FIG. 2, a 3D-MV die 20 comprises at least a 3D-MV array 16 and a peripheral circuit 18. The 3D-MV array 16 comprises a plurality of vertical memory strings 16X, 16Y. Each memory string (e.g., 16X) comprises a plurality of vertically stacked memory cells (e.g., 8a-8h). These memory cells are coupled by at least a vertical address line. Each memory cell (e.g., 8f) comprises at least a vertical transistor, with a gate 6, an information storage layer 7 and a vertical channel 9. The gate 6 of each memory cell (e.g., 8f) on a vertical memory string forms a BEOL level. In this example, the 3D-MV array 16 comprises eight BEOL levels, i.e., the memory levels 8a-8h. 
Because the vertical memory strings 16X, 16Y in 3D-MV include a portion of the substrate 0A and no peripheral circuit can be formed there-under (FIG. 2), the 3D-MV die 20 could only comprise outside-array peripheral circuit 18. This is different from 3D-MH (FIG. 1A), which could comprise an under-array peripheral circuit. The peripheral circuit 18 for the 3D-MV array 16 comprises substrate transistors 0t and substrate interconnects 0i. The substrate transistors 0t are conventional (horizontal) transistors formed in the semiconductor substrate 0. The substrate interconnects 0i are the interconnects for the substrate transistor 0t. In this example, the peripheral circuit 18 comprises two BEOL levels, i.e., the interconnect levels 0M1, 0M2.
The prior-art 3D-MV is an integrated 3D-MV, whose 3D-MV array 16 and peripheral circuit 18 are integrated into a single 3D-MV die 20. Because their manufacturing processes are not compatible, the 3D-MV array 16 and its peripheral circuit 18 are formed separately. Accordingly, the 3D-MV die 20 of FIG. 2 comprises ten BEOL levels, including eight memory levels for the 3D-MV array 16 and two interconnect levels for the peripheral circuit 18.
It is a prevailing belief in the field of integrated circuit that more integration is better, because integration lowers cost and improves performance. However, this belief is no longer true for 3D-MV. First of all, because the vertical memory strings 16X, 16Y comprises significantly more BEOL levels than the peripheral circuit 18, integrating would force a relatively simple peripheral circuit 18 to use the expensive BEOL manufacturing process of the 3D-MV array 16. This increases the overall 3D-MV cost. Secondly, as the 3D-MV 20 is optimized for its 3D-MV array 16, the performance of its peripheral circuit 18 is sacrificed. For example, the peripheral circuit 18 may comprise just a small number of interconnect levels (e.g., as few as two), or comprise high-temperature interconnect materials whose speed is generally slower (e.g., tungsten for conductive material and silicon oxide for insulating material).This degrades the overall 3D-MV performance.